The present invention relates to a registered memory module and, more particularly, to a memory module having a delay locked loop (hereinafter, abbreviated to a DLL) circuit in a register.
A technology using stub bustopology for a DQ bus and a clock bus (hereinafter, referred to as related art) has been proposed for purpose of response to a high frequency band. In the related art, an external clock signal WCLK transmitted from a chip set (or memory controller) is distributed into a plurality of memory devices arranged on a substrate of each memory module. Meanwhile, in the related art, a command/address (hereinafter, abbreviated to a C/A) signal transmitted from the chip set to the memory module is latched to a C/A register (hereinafter, referred to as a register) arranged on the substrate of each memory module. Thereafter, the latched C/A signal is distributed to a corresponding memory device as an internal C/A signal.
Currently, a large number of types of memory modules having four to eighteen memory devices, depending on whether or not an ECC function is provided or whether or not which capacity is realized, have come into a market. Operating frequencies of the memory device mounted on one memory module are varied.
On the other hand, in the related art, when the number of mounted memory devices is different if the operating frequency is constant, methods are used whereby loads on the memory modules are forcedly matched and an individual register is utilized every mounted memory device. This is because a set-up time and a hold time are held to be appropriate in a flip-flop forming a latch circuit.
The efficiency of parts is deteriorated when designing and manufacturing another register only because the number of mounted memory devices is different despite the same operating frequency.
In addition, in the related art, as will obviously be understood based on a fact that the change in number of mounted memory devices requires the individual register as mentioned above, it is difficult that the single register responds to a wide operating frequency band.
Under the above-mentioned circumstances, it is desired that a register independent of the number of mounted devices is provided so as to improve the efficiency of parts. Further, it is desired that a register corresponding to a wide frequency band (e.g., a clock frequency of 200 to 300 MHz) is provided.
Accordingly, it is one object of the present invention to provide a register which can appropriately generate an internal C/A signal independently of the number of mounted memory devices as long as an operating frequency is constant.
It is another object of the present invention to improve the above-mentioned register which can correspond to a wide frequency band.
The present applicants thought as follows. In order to obtain a register which can generate an internal C/A signal independently of the number of mounted memory devices when an operating frequency is constant, the register comprises therein a DLL circuit which controls the delay in accordance with an external clock signal distributed from a chip set and generates an internal clock signal for prescribing latch operation. The latch operation is performed by the above-generated internal clock signal because a deviation (propagation delay) between the external clock signal and the C/A signal in the memory device is absorbed. However, when the synchronous C/A signal deviated from the external clock signal with a half period is latched by the internal clock signal, there is a problem in that a set-up time and a hold time cannot sufficiently be assured in the latch operation.
To solve the above-mentioned problem, the present applicants further thought as follows. The C/A signal may temporarily be latched by the external clock signal and the latched output may be latched again by the internal clock signal.
Next, the present applicants research a method by which the register can correspond to a wide frequency band independently of the number of mounted memory devices. As a research result, in the register, as a pre-processing for latching the C/A signal, a period of the C/A signal is n2 times (e.g., two or four times) and thereafter the resultant signal is latched. Thus, the hold time and the set-up time can sufficiently be assured for the latch operation in the register corresponding to a different operating frequency.
The present invention, in order to solve the above-mentioned problems, based on the foregoing, provides a register for a registered memory module and a memory module having the register.
The register of the present invention is mounted on a memory module including a plurality of memory devices, receives an external clock signal from a chip set outside the memory module and a command/address (hereinafter, abbreviated to a C/A) signal indicated by a plurality of continuous values, and generates an internal C/A signal for the memory device.
According to a first aspect of the present invention, there is provided a register comprising: a delay locked loop (hereinafter, abbreviated to a DLL) circuit receiving an external clock signal, adjusting the amount of delay, and generating an internal clock signal; a first latching unit for latching a C/A signal in accordance with the external clock signal and generating a first intermediate C/A signal; a second latching unit for latching the first intermediate C/A signal in accordance with the internal clock signal and generating a second intermediate C/A signal; and an output unit for outputting the internal C/A signal in accordance with the second intermediate C/A signal.
According to a second aspect of the present invention, there is provided a register comprising: a DLL circuit for receiving an external clock signal, adjusting the amount of delay, and generating an internal clock signal; and a rate converting unit. The rate converting unit receives a C/A signal and generates first and second intermediate C/A signals having a half frequency of the C/A signal. The first intermediate C/A signal has one of odd-th and even-th C/A signals, and the second intermediate C/A signal has the other of the odd-th and even-th C/A signals. The register according to the second aspect further comprises a latching unit for latching the first and second intermediate C/A signals in accordance with the internal clock signal and generating third and fourth intermediate C/A signals, and an output unit for alternately selecting the third and fourth intermediate C/A signals by a half frequency of the internal clock signal and outputting the internal C/A signal.
According to a third aspect of the present invention, there is provided a register comprising: a DLL circuit receiving an external clock signal, adjusting the amount of delay, and generating an internal clock signal; and a rate converting unit. The rate converting unit receives a C/A signal and generates first to n-th intermediate C/A signals having a frequency of 1/n2 (where n is a natural number and is not less than 2) of the C/A signal. The first to n-th intermediate C/A signals have values that are sequentially selected at intervals of (nxe2x88x921) values among from the plurality of continuous values of the C/A signal. The register according to the third aspect of the present invention further comprises a latching unit for latching the first to n-th intermediate C/A signals in accordance with the internal clock signal and generating (n+1)-th to 2n-th intermediate C/A signals, and an output unit for sequentially selecting the (n+1)-th to 2n-th intermediate C/A signals by a frequency of 1/n2 of the internal clock signal and outputting the internal C/A signal.
In the present invention, there is provided a memory module comprising a register according to any of the first to third aspects and a plurality of memory devices, all of which are mounted on a single substrate.
Further, in the present invention, there is provided the memory module wherein the number of memory devices is not less than 4 and is not more than 18.
Furthermore, in the present invention, there is provided a memory system comprising the memory module and a chip set.
In addition, in the present invention, there is provided a memory system comprising a register provided for a memory module including a plurality of memory devices, for receiving an external clock signal and a C/A signal indicated by a plurality of continuous values from a chip set outside the memory modules and generating an internal clock signal of the memory device. The register comprises a DLL circuit for receiving the external clock signal, adjusting the amount of delay, and generating an internal clock signal. The necessary number of external clocks from a rising edge of the external clock signal for fetching the C/A signal to the register to a timing for fetching the internal C/A signal corresponding to the C/A signal into the memory device by the external clock signal is at least 2.0.